1. Technical Field of the Invention
The present invention pertains generally to the field of radio frequency (RF) power transistor devices and, more specifically, to techniques for providing ground signal paths in a laterally diffused metal oxide semiconductor (LDMOS) power transistor package assembly.
2. Description of Related Art
The use of RF power transistor devices as signal amplifiers in wireless communication applications is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services, the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz frequencies. At such high frequencies, laterally diffused, metal oxide semiconductor (LDMOS) transistors have been preferred for power amplification applications, e.g., for use in antenna base stations.
A typical LDMOS power package generally comprises a plurality of electrodes formed on a semiconductor die, each electrode comprising a plurality of transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals formed on the surface of the die. A common ground (source) terminal substrate is formed on the underlying side of the die. The die is attached, e.g., by a known eutectic die attach process, to a metal flange serving as a combined ground current reference, heat spreader and mounting device for the package. A thermally conductive, but electrically isolating, e.g., aluminum oxide, xe2x80x9cwindowxe2x80x9d substrate is attached to the flange, surrounding the die. Respective input and output lead frames are attached, e.g., at opposing ends, to a top surface of the window substrate, electrically isolated from the flange.
The input and output lead frames are coupled to the respective electrode input and output terminals via respective input and output transmission paths, which may also include one or more impedance matching elements interposed between the respective lead frames and electrode terminals.
Impedance matching between circuit elements external to the power package and the respective electrode terminals on the die is crucial to proper operation, especially at high operating frequencies. Another crucial factor is providing a uniform ground potential for the power package and the surrounding circuitry.
By way of illustration, FIG. 1 is a simplified schematic of a known LDMOS power transistor device 10. The device 10 comprises a plurality of parallel transistors 12, having a common input (gate) lead 14, a common output (drain) lead 16, and a common ground (source) 18 through an underlying substrate.
FIGS. 2-3 depict a power package 20 employing such an LDMOS device 10 and mounted in a cut-away area 36 of a heat sink 22, e.g., as part of an amplifier circuit. The power package 20 includes a mounting flange 26 attached to the heat sink 22 by a pair of mounting screws 24. A single layer printed circuit (PC) board 28 is also secured to the heat sink 22, substantially surrounding the power package 20. The PC board 28 includes a conductive top surface 30, a layer of dielectric material 32, and a conductive bottom surface 34, respectively. The bottom surface 34 and attached heat sink 22 form a reference ground plane for both the LDMOS device 10, which is attached to the top surface 27 of the mounting flange 26, and other amplifier circuit elements (not shown) located on the top PC board surface 30.
A dielectric substrate 38 is attached to the top surface 27 of the mounting flange 26, the substrate 38 defining a window surrounding an exposed area of the top surface of the flange where LDMOS device 10 is attached. Respective bond wires 40 and 42 extend from the input (gate) and output (drain) terminals (14) and (16) of the LDMOS device 10 to respective input and output lead frames 44 and 46 attached to the window substrate 38. The input and output lead frames 44 and 46 extend from opposite sides of the substrate 38, and are connected by respective solder welds 48 and 50 to corresponding conductive paths 31 and 33 formed on the top surface 30 of the PC board 28.
Notably, the power package 20 depicted in FIGS. 2-3 is simplified, in that impedance matching elements commonly inserted in the transmission path between the respective leads 44 and 46 and electrode terminals (14) and (16) are omitted. Further, the power package 20 will normally have a protective cover, which is also omitted for ease in illustration.
FIG. 4 depicts the current signal paths through the PC board 28 and power package 20. An input signal 52 flows between input matching elements (not shown) and the package input lead 44, via a first conductive path formed in the top layer 30 of the PC board 28 and the solder weld 48. Similarly, an output signal 54 flows between output matching elements (not shown) and the package output lead 46, via a second conductive path formed in the top PC board layer 30 and the solder weld 50. A ground signal 56 flows from the ground terminal (18) underlying the device 10, in all directions across the top surface 27 and down the sides 58, respectively, of the mounting flange 26, across a peripheral surface 60 of the cut-away area 36 of the heat sink 22, back up the sides 59 of the cut-away area 36, and then through the bottom layer 34 of the PC board 28.
In such high frequency amplifier applications, there can be a significant amount of current. Because of the path losses for these currents, there is a voltage drop created, which causes signal loss, decreased efficiency, and reduces isolation between ports.
Thus, it would be desirable to provide an LDMOS power package with an improved ground signal path, especially for use with multi-layer PC board applications.
In accordance with the present invention, an LDMOS power package is provided with multiple ground signal paths. In a preferred embodiment, the power package includes a conductive mounting flange, with a dielectric substrate attached to the mounting flange. An inner surface of the substrate defines a window exposing a portion of the mounting flange. A silicon die is attached to the exposed portion of the mounting flange, the die having a plurality of transistors formed thereon, the transistors having respective input, output and ground terminals, the ground terminal electrically coupled to the mounting flange. An input lead frame is attached to the top surface of the substrate, isolated from the flange, and electrically coupled to the respective transistor input terminals. An output lead frame is attached to the substrate, isolated from the flange, and electrically coupled to the respective transistor output terminals. A ground lead frame is attached to the substrate, wherein the input, output and ground leads are electrically isolated from one another.
In another aspect, the present invention is directed to an LDMOS power package that includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths electrically couple the top surface of the mounting flange to the dielectric substrate.
In another aspect, the present invention is directed to an assembly that includes a heat sink; a printed circuit (PC) board having a top conductive surface and a dielectric substrate coupled to the heat sink to form a reference ground plane; and a laterally diffused metal oxide semiconductor (LDMOS) power package. The power package includes a conductive mounting flange mounted on the heat sink and connected to the dielectric substrate. A plurality of transistors are mounted on a top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate.
As will be apparent to those skilled in the art, other and further aspects and advantages of the present invention will appear hereinafter.